Intel Processors: MCS-4, MCS-8, MCS-85, x86: IA-16, IA-32, IA-64.

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Processor Date Performance (MIPS)
(instr. set)
Registers
Size (no-bits)
(tot regs)
Data/Addr bus
PC bus speed
CPU max I/O
Clock (Hz)
Bus (Hz)
Power (v/W)
Transistors (106)
(mm/layers)
(mm2)
Max Mem Cap
Physical/Virtual
(L1/L2 Cache)
No. pins
(pack)
Notes
4004
4040
1971
1972
0.006
(45)
16x4b GP 4/12 bits
(? B/s)
.108 MHz
(-15v/30mW)
0.0023
(10mm pMOS)
(12mm2)
2Kb code-ROM
640b data-RAM
16-DIP First microprocessor chip: MCS-4: 4001-ROM, 4002-RAM, 4003-shift-reg, 4004-CPU: 16x4b-regs+4b-Acc+12b-PC+3L-stack, 4b-BCD-ALU, test+reset pin, +32x4b I/O ports. intr cycle: 11-22ms (perf » ENIAC multi-million, 18K tubes, 1946). Mem manuf Intel (f 1968), starts 12-chip japan-calculator Busicom project (1969), proposes 4-chip system (1970), bought rights ($60K) and sell chips (1971). 4040: 24-pin, +14 inst, 8L-stack, 8K-ROM & INT. Apps (BCD arith): calculators & embedded control, eg SIM4: first microcomputer (1972), elevators, NASA Pioneer. [M$2 -> $0.001, $200]
8008 1972 .06
(48)
7x8b GP 8/14 bits
(? B/s)
.2-.8 MHz
(5,-9v)
.002-.0035
(10mm pMOS)
16Kb 18-DIP First 8-bit CPU chip. MCS-8: 8L-stack, 2 clocks, 2 voltages, first vect-interrupt, requires 20-40 interfacing chips, 8-in/24-output 8b ports. intr cycle: 12-30ms. Developed in tandem with 4004. First computer kits: French Micral & US$565 Scelbi-8H (1973), Mark-8 (1974). Lic manuf: Siemens. Apps (data/char manip): ASCII terminals (original Intel's CTC-Datapoint sponsor), calculators (first Seiko user prog calculator). [$120]
8080
8080A
1974
1976
0.29
(78)
10x8/16b 8/16 bits
(? B/s)
2-3 MHz
(-5,5,12v/1.5W)
.0045,.006
(6mm pMOS/nMOS)
64Kb 40-DIP MCS-8: 10X 8008, 2 clock, 3 volt, 16b addr, ext stack, mult interrupt, 256 I/O port, 6 support-chip. intr cycle: 2ms. Good marketing, manuals & develop tools. First Home Computer: MITS Altair 8800 ($439,1975). BASIC for Altair (Gates & Allen). CP/M for 8080 (Kindall,1975). Competition: Z80 (8080 compatible, 8.5K trx, 26+ reg, 158 instr, 2-8MHz, $200->50, 1976), 6800 (first 5v-only, 4K trx, 6 reg, 72 instr, 1-2MHz, $200->70, 1974), 6502 (5 regs, 56 instr, 9K trxs, 1-2MHz, first $25, 1975). Manuf: AMD, TI, NI, NEC, Mitsubishi, Siemens. App: computer kits, video games, auto engines, traffic lights. [$360->180->70 -> $10-15]
8085 1976 0.37
(80)
10x8/16b 8/16 bits
(? B/s)
3-6 MHz
(5v/1.5W)
0.0065
(3mm nMOS)
64Kb 40-DIP MCS-85: 8080 compatible, first single-clock, vectored int, first single-5v, first on-chip: serial I/O, clock generator, bus controller. intr cycle: 1.3ms. Min system of 3 IC's: CPU, RAM/IO, ROM. Good support-chips. Lost 8-bit war (late & expensive). Manuf: AMD, NEC, Toshiba, Mitsubishi, Siemens, OKI. [$100?->$15]
8086
8088
1978
1979
0.33-0.75
(95/300)
14x16b 16,8/20 bits
(2-3 MB/s)
(2-10Mb/s)
5-10 MHz
(5-10 MHz)
(5v/2.5W)
0.029
(3mm nHMOS)
(33mm2)
1Mb 40-DIP G1. First 16-bit x86 chip. 10X 8080. inst cycle: <½ ms (perf » DEC PDP-11/60, $40K, 1977). CISC arch, parallel EU & BIU. 1-stg pipeline 6b prefetch-queue. 64K I/O 8/16b ports. 256 ints. First 64K seg-mem. Integer full-arithmetic. String ops. Low-cost 8088 (16b CPU, 8b data bus, 4b p-queue, 1979). 8087 num coproc (45K trxs, +68 instr, 8-80b regs, 40-pin, 3W, 100X 8086, 1980). First IBM PC (1981), PC/XT (1983). 8b ISA bus. Competition (1979): M68000, Z8000. First x86 clone: NEC V20 & V30 (20-30% faster 8086, 1985). Lic manuf: AMD, Harris, Mostek, Fujitsu, NEC, Toshiba, OKI, Siemens. [$360 -> $5-10]
80186
80188
1982
1990
1
(105)
14x16b 16,8/20 bits
(? B/s)
6-25 MHz
(2.7-5v/1.5W)
0.055
(3,1mm nMOS)
1Mb 68-LCC
80-PGA
G2. 2X 8086. On-chip integration: PIC, 3 timers, 2 DMA, clock, serial, I/O ports, support logic (replace up to 20 chips). +10 instr. Fault tolerance protection. Only PC Tandy 2000 use it. Enhanced 186Ex fam: 25 Mhz, 1mm, CHMOS, 3v, 1990. App: Embedded processor, eg disk controller, LAN card. [$15-25]
80286 1982 0.9-2.6
(110)
15x16b 16/24 bits
(4-12 MB/s)
(10-38 MB/s)
6-20 MHz
(6-12 MHz)
(5v/2-3.3w)
0.134
(1.5mm HMOS)
(47 mm2)
16Mb/1Gb 68-LCC
68-PGA
G2. First "real" processor. 2-6X 8086. inst cycle: <¼ ms (perf » DEC VAX-11, $200K, 1977; mVAX-II, 1985). Real & protected mode. On-chip MMU, virtual mem (1Gb), 4-rings & multitasking. 1-stg pipeline 8b p-queue. New sys regs: MSW, GDTR, LDTR, IDTR, TR. 80287: 10MHz, 3W, 80-pin, 1983. ISA bus: 16b, 8MHz, 5MB/s. IBM PC/AT (1984), PS/2 Mod 50. DOS: as faster 8086; OS/2: ltd protected-mode. Lic manuf: AMD, Harris, IBM, Siemens. [$350->$10]
80386 DX,
SX, SL
1985
1988
1990
1991
2.5-11
(120+)
18x32b 32/32 bits
16/24 bits
(32-50 MB/s)
(60-150 MB/s)
16-33 MHz
(8-16 Mhz)
(3,5v/2,5W)
0.275,0.855
(1.5,1mm CHMOS)
(43mm2)
16Mb/256Gb
4Gb/64Tb
32-256K L2
132-PGA G3. First 32-bit x86 chip. 10-20X 8086, 3X 286. Most instr exec 2 cycles (4-stg pipeline 16b p-queue). Extend 32b regs, 286 sys-regs plus FS, GS, CR0-3 & debug regs. First mem cache: TLB buffer & L2. Real, protected & v86 mode. "Flat" 32b mem model (break 64K/1M barrier). Built-in "true" multitasking & 4K-page/64K-seg virtual mem. EISA bus: 16MHz, 32MB/s. 387: 20-33MHz, 68-pin, 1986. Low-cost SX: 16b data-bus & 24b addr-bus (max 16Mb). Low-power SL for laptops. Compaq: first 386 PC. 386 clones: AMD-40Mhz, IBM SLC (80% faster, 8K-L1). Linux: first 386 OS kernel. [$150-300 -> $15-30]
80486 DX,
SX, DX2, DX4
1989-
1994
16-70 20x32b
8x80b FPU
32/32 bits
(50-132 MB/s)
(90-200 MB/s)
16-100 MHz
(16,25,33Mhz)
(3.3,5v/5W)
1.2-1.6
(1,.8,.6mm/4 CHMOS)
(81,345mm2)
4Gb/64Tb
8,16K L1
256K L2
168-PGA 176-TQFP 208-SQFP G4. 30-60X 8086. First on-chip L1 cache & math coprocessor. Most inst exec 1 cycle (5-stg pipeline). Low-cost SX: a 486 with a non-functional math unit. DX2/DX4: 2/3X internal speed. Better PC motherboards. VESA bus: 32b, 33MHz, 132MB/s, 1992. Good x86 clones: AMD DX4/120, Cyrix DX4/100, IBM, TI, UMC, NextGen, etc. [$900 -> $10-40]








Intel Processors: MCS-4, MCS-8, MCS-85, x86: IA-16, IA-32, IA-64.

[4004] [8008] [8080] [8085] [8086] [8088] [80186] [80286] [80386] [80486] [Pentium] [Pentium Pro] [Pentium II] [Pentium III] [Pentium 4] [Itanium] More..

Processor Date Performance (MIPS)
(instr. set)
Registers
Size (no-bits)
(tot regs)
Data/Addr bus
PC bus speed
CPU max I/O
Clock (Hz)
Bus (Hz)
Power (v/W)
Transistors (106)
(mm/layers)
(mm2)
Max Mem Cap
Physical/Virtual
(L1/L2 Cache)
No. pins
(pack)
Notes
Pentium
MMX
Mobile
Overdrive
1993- 1998 100-250
iSpec95
2-7
20x32b GP
8x80 FPU
8x64 MMX
64/32 bits
(264 MB/s)
(450-500 Mb/s)
60-266 MHz
(50,60,66Mhz)
(2.8-5v/3-16W)
3.1,4.5
(.8-.25mm/4 BiCMOS)
(90-296mm2)
4Gb/64Tb
16K L1
256-512K L2
273-PGA 296-PGA 320-TCP G5. Quasi-superscalar arch: 2 exec 5-stg pipeline (2 instr/cycle). 3-5X 486, 200X 8086. Branch prediction. CPUID. On-chip cache (8K-data, 8K-code) & math unit (2-int, 1-fpu 8-stg pipeline). No out-of-order exec. Low-perf 16-bit code. MMX (Matrix Math eXt, Multi-Media eXt, 1995): +57 instr. Dual CPU support. PCI bus: 64b, 66MHz, 264MB/s. Huge gap CPU/bus speed. FDIV bug episode. CPU-fan required. First mobile: low-power CMOS (2.8v). desktop-market:end-1995. notebook-market:1996. x86 clones: AMD K5, Nx686, Cyrix 6x86, 6x86MX, IDT cheap, low-power C6 WinChip, etc. [M$50-60, $500-900 -> $50-90]
Pentium Pro 1995- 1997 200-300
iSpec95
6-9
22x32b GP
8x80b FPU
64/36 bits
(528 MB/s)
(528 MB/s)
120-200MHz
(60,66 MHz)
(3.3v/25-43W)
5.5, 15.5 (256K L2)
(.5,.35mm/4 BiCMOS) (308,196mm2)
64Gb/64Tb
16-32K L1
256K-512K L2
387-MCM 387-PGA G6. New P6 arch: RISC core with x86 translation, 3-way (3 inst/cycle, 6 mOPs/cycle) full-superscalar 12-stg superpipeline. 3/5 fixed-length "micro-ops" (mOP) Register renaming. Out-of-order 5 exec units (2-int, 2-fpu, 1-ldst). Embedded L2 cache (64b data bus, 4 parallel access). 50% faster same-speed Pentium: hi-perf 32-bit, low-perf 16-bit. First x86 higher-perf than other RISC-32. SMP: 2/4 proc. Competitors: AMD K6, Cyrix M2. [M$150-180, $500-1K -> $75]
Pentium II
Xeon
Celeron
Mobile
1997- 1999 350-460
iSpec95
9-19
22x32b GP
8x80b FPU
8x64b MMX
64/36 bits
(528 MB/s)
(528 MB/s)
233-450MHz
(66,100MHz)
(1.5-2.8v/8-40W)
7.5, 27.4 (256K L2)
(.35,.25,.18mm/5 CMOS)
(131,203mm2)
64Gb/64Tb
32K L1
128K-1M L2
528-LGA 615-BGA 242-SEC 330-SEC G6. P6 arch: 3-way (3 inst/cycle) superscalar 14-stg super-pipeline. Dual independent bus. Intel patented SEC cartridge. Incorpores 2 MMX units. 16K data, 16K code L1 cache. L2 cache half clock speed. FPU: 32/64/80b format. Faster 16-bit code performance. Faster motherboards: AGP bus (1998) 100MHz, 528MB/s. SMP: 2/4/8 proc. Multiple low-power states. On-die temp sensor. Xeon: PII on steroids (1M L2). Celeron: a stripped down PII (128K L2), up to 800MHz. Competitors: AMD K6-2 MMX 3DNow. [$800 -> $40-80]
Pentium III
Xeon
Celeron
Mobile
1999- 2001 500-2700
iSpec95
18-40
22x32b GP 8x80b FPU 8x64b MMX 8x128b XMM 64/36 bits
(1GB/s)
400MHz-1GHz
(100,133MHz)
(1.1-2v/<1-20W)
9.5-28.1 (256K L2)
(.35-.18mm/6 CMOS)
(80-385mm2)
64Gb/64Tb
32K L1
128K-2M L2
370-PGA2 495-BGA2 330-SEC G6. P6 arch. First 1GHz x86 (perf » Cray YMP, 1-2BIPS, $1M, 1988). On-die L2 cache full-clock speed (Advanced Transfer Cache). Streaming SISD (SSE): expanded MMX +70 instr. SMP: 2/4 proc. Exec units: 2-ALU/MMX/SSE, load, store data/addr, pipelined FPU. CPU serial number. Multi-transaction, dual-indep bus. Mobile: Ultra-low volt, speed-step tech. Tualantin: 1.2GHz, 256K-L1, 1.4v, 0.13mm, 3.3 BIPS, $300, 2001. Competitors: AMD K7 Athlon/Duron, VIA Cyrix III. [$1000 -> $50-250]
Pentium 4
Xeon
2000 2001 3000-3700
i/f Spec2K
640/704
30x32b GP 8x80b FPU 8x64b MMX 8x128b XMM 64/36 bits
(3 GB/s)
1.3-2GHz
(400MHz)
(1.7v/50W)
42
(.18,.13mm CMOS)
(217 mm2)
64Gb/64Tb
8/12K L1
256K-2M L2
423-PGA 478-PGA 603-OLGA G6. New NetBurst arch: First 2GHz CPU. Hi-perf IA-32 (30-90% faster PIII, close to Alpha 21264 833Mhz), 20-stg hyper-pipelined (up to 6 inst/cycle), 12K micro-op trace cache. Deep, out-of-order, speculative exec-unit (up to 126 inst, 40 ld, 24 st). Adv dynamic-exec & branch-prediction. Full-speed, unified 8-way L2 on-die cache. ALUs at 2X CPU speed allows integer instr exec in ½ clock cycle. Expanded renaming regs, SSE2 SIMD extensions (+144 instr), 400 Mhz bus (4x100Mhz bus). No SMP support. Built-in self-test, perf & thermal monitor. Competitor: AMD K7 Thunderbird/Athlon/XP. [$650 -> $120-550]
Itanium 2001 i/f Spec2K
370/715
256x128b GP/FPU 64/44 bits
(2.1 GB/s)
733-800MHz
(?MHz)
(3.3v/120W)
30
(.18,.13mm CMOS)
(? mm2)
16Tb/254
2x16K L1 96K L2 2-4M L3
418-PAC G7. First 64-bit x86 chip. 7-year join-effort Intel-HP(Alpha) design team. IA-32 compatible (including MMX/SSE). 15 exec units 10-stg pipeline: 2-int, 2-fp, 2-ldst, 3-branch (up to 4 ALU-inst/cycle) 256 general & fp 128-bit regs. 244 phys addr (16 Terabytes) & 254 virtual addr (16 Petabytes), Full speed 2/4Mb L3 cache. Built-in prog EEPROM. 6-wide EPIC (explicitly parallel instr computing), predication, speculation, register managment under compiler support. SMP:2-512 proc. Windows XP 64-bit Ed. [$1200-4200]

[4004] [8008] [8080] [8085] [8086] [8088] [80186] [80286] [80386] [80486] [Pentium] [Pentium Pro] [Pentium II] [Pentium III] [Pentium 4] [Itanium] More..

Alberto Pacheco, alberto@acm.org, 2001/10/12.